1. Field
The embodiment(s) discussed herein are related to optical modulation devices and optical modulation methods for performing modulation by a plurality of modulators.
2. Description of the Related Art
In recent years, with an increase in transmission traffic, the demand for introduction of a next-generation 40 Gbps optical transmission system has been growing. Moreover, a 40 Gbps optical transmission system requires a transmission distance and/or a spectral efficiency equivalent to those of a typical 10 Gbps optical transmission system. As a way for realizing such a next-generation 40 Gbps optical transmission system, researches have been conducted on RZ-DPSK (Return to Zero Differential Phase Shift Keying) and/or CS (Carrier-suppressed) RZ-DPSK modulation scheme having high OSNR (Optical Signal Noise Ratio) tolerance and/or nonlinearity tolerance.
FIG. 12 is a block diagram illustrating a configuration of a typical optical modulation device. An optical modulation device 1200 illustrated in FIG. 12 is an optical modulation device that uses an RZ-DQPSK (RZ-Differential Quadrature PSK) scheme at about 40 Gbps. An RZ-DQPSK scheme is expected as a modulation scheme for a next-generation optical transmission system because the RZ-DQPSK scheme has a narrow spectrum (high spectral efficiency) feature (see Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2004-516743 and Japanese Unexamined Patent Application Publication No. 2007-158415 described below, for example).
A phase modulator 1210 has two Mach-Zehnder interferometers constituting an I arm and a Q arm, and serves as a DQPSK modulator for performing quadrature phase modulation. The I and Q arms each perform phase modulation at 20 Gbps based on a data signal input to each of the I and Q arms. In the phase modulator 1210, one of the respective signals, on which phase modulation has been performed by the I and Q arms, is phase-shifted (delayed) by π/2, and is multiplexed with the other signal.
The phase modulator 1210 outputs, as a DQPSK signal, the multiplexed light to an RZ modulator 1220. The RZ modulator 1220 performs, based on a second clock signal input thereto, RZ modulation (pulse carving) on the phase modulated signal output from the phase modulator 1210. The RZ modulator 1220 outputs, as an RZ-DQPSK signal, the RZ modulated signal to the outside.
Decision circuits 1231 and 1232 each serve as a circuit for performing waveform shaping on a data signal input thereto from the outside. The decision circuits 1231 and 1232 each make a decision on the input data signal in accordance with the timing of a first clock signal input thereto, thereby performing waveform shaping on the data signal degraded in a circuit at a preceding stage of the decision circuits 1231 and 1232. The decision circuits 1231 and 1232 output the data signals based on the decision to the phase modulator 1210.
However, in the optical modulation device 1200 described above, the amount of phase delay in a circuit is changed due to temperature variation and/or aging variation (such as age deterioration of the circuit). Because of this change, there arises a problem that the relative phases of the data signal input to the phase modulator 1210 and the second clock signal input to the RZ modulator 1220 are each shifted from the optimal value. If such a phase shift has occurred, the timing of modulation by the phase modulator 1210 and that of modulation by the RZ modulator 1220 with respect to the light to be modulated are deviated from each other.
Specifically, there occurs a phase difference between the DQPSK signal (denoted by the reference numeral 1221 in FIG. 12) output from the phase modulator 1210 to the RZ modulator 1220, and the second clock signal (denoted by the reference numeral 1222 in FIG. 12) input to the RZ modulator 1220. Therefore, the timing of pulse carving by RZ modulation is deviated from the timing of modulation of the DQPSK signal, resulting in optical signal degradation.
FIG. 13 is a graph describing a relationship between the phase difference and Q value penalty. In FIG. 13, the horizontal axis represents the phase difference [ps] between the DQPSK signal output from the phase modulator 1210 to the RZ modulator 1220, and the second clock signal input to the RZ modulator 1220. The vertical axis in FIG. 13 represents the Q value penalty [dB] of the optical signal output from the RZ modulator 1220. A characteristic 1302 represents a change in the Q value penalty of the optical signal with respect to the phase difference represented by the horizontal axis.
As indicated by the characteristic 1302, the greater the phase difference between the DQPSK signal and the second clock signal, the greater the Q value penalty of the optical signal. A threshold value 1303 is provided as a threshold value at which the Q value penalty represented by the vertical axis becomes 0.1 dB. If the Q value penalty is allowed to 0.1 dB, the allowable phase difference range is between about −6 ps and about +6 ps. In this regard, consideration may be given to the idea of compensating the phase difference between the DQPSK signal and the second clock signal by using temperature monitor information (see Japanese Unexamined Patent Application Publication No. 2007-158415, for example). However, in this case, there arises a problem that information on temperature dependence, aging variation characteristic, individual variation, etc. is needed in advance for feedforward control, thus making it difficult to perform high-precision phase difference control.
Further, in this regard, consideration may be given to the idea of controlling the relative phases of the data signal input to the phase modulator 1210 and the second clock signal input to the RZ modulator 1220, thereby compensating the phase difference between the DQPSK signal input to the RZ modulator 1220 and the second clock signal input to the RZ modulator 1220.
However, if the phase of the first clock signal is greatly changed in order to change the phase of the data signal input to the phase modulator 1210, the phase difference between the data signal and the first clock signal in each of the decision circuits 1231 and 1232 is increased. As a result, it becomes difficult to make a decision on the data signal by each of the decision circuits 1231 and 1232. Further, since the phase difference between the data signal and the first clock signal also varies depending on temperature variation and/or aging variation, the phase margin, which allows a decision to be made on the data signal, is small.
Therefore, it has been difficult to change the phase of the data signal input to the phase modulator 1210. In this regard, consideration may be given to the idea of changing the phase of the second clock signal in order to control the phase difference between the data signal and the second clock signal.
FIG. 14 is a diagram describing an operation performed in changing the phase of the second clock signal. In FIG. 14, the horizontal axis represents time. A waveform 1411 represents the data signal (DQPSK optical signal) input to the RZ modulator 1220. A dotted line 1421 represents the center of one cycle of the data signal. A waveform 1412 represents the second clock signal input to the RZ modulator 1220. And a dotted line 1422 represents the center of one cycle of the second clock signal.
The compensation of the phase difference between the data signal and the second clock signal is equivalent to the bringing of the dotted line 1421 and the dotted line 1422 close to each other. When the phase of only the second clock signal is changed, the delay amount of the second clock signal (indicated by the left-pointing arrow) needs to be increased, and a significant delay variable range is needed in a phase shifter for delaying the second clock signal.
At a frequency as high as 20 GHz or more in particular, it is technically difficult to increase the delay variable range of a phase shifter, and a plurality of phase shifters have to be provided in order to realize an increase in the delay variable range. In addition, in this case, there arises a problem that the insertion loss of the second clock signal is increased. Furthermore, there arises a problem that the cost of circuits such as a new phase shifter, a driver amplifier, etc. is increased.